2024-03-29T15:14:14Z
https://repository.dl.itc.u-tokyo.ac.jp/oai
oai:repository.dl.itc.u-tokyo.ac.jp:00001840
2022-12-19T03:43:20Z
34:105:262
9:233:234
低オーバヘッド セキュリティ・タグ・アーキテクチャ
Low-overhead security-tagged architecture
Kim, Daewung
5657
548
修士(情報理工学)
A tagged architecture is a system that applies tags on data, recently used in the field of information security./ The previous studies using tagged architecture mostly focused on how to utilize tags, not how the tags are implemented. A naive implementation of tags simply adds a tag field to every byte of the cache and the memory. Such technique, however, results in a huge hardware overhead and performance degradation, as well as is unable to support variable-length tags./ This thesis proposes a low-overhead security-tagged architecture that supports variable-length tags. We achieve our goal by separating tag and data completely. The proposal technique is composed of two parts, separation in storage and separation in execution./ First, in the separation of storage, we exploiting some properties of tag, the non-uniformity and the locality of reference. Our design includes a use of uniquely designed multi-level table and various cache-like structures, all contributing to exploit these properties./ Second, in the separation of execution, we suggest to propagate tags after the completion of execution of data. This allows to have dedicated tag register file and L1 tag cache, so that prevent to increase in the access latency for register and cache. Under simulation, our method was able to reduce the memory overhead to 3.48% of the naive implementation, and 4.96% of IPC degradation compared with conventional computer system, in addition to supporting variable-length tag.
thesis
2009-03-23
2009-03-23
application/pdf
https://repository.dl.itc.u-tokyo.ac.jp/record/1840/files/kim.pdf
eng