2024-03-28T11:13:36Z
https://repository.dl.itc.u-tokyo.ac.jp/oai
oai:repository.dl.itc.u-tokyo.ac.jp:00004989
2022-12-19T03:46:42Z
6:260:318
9:233:280
高速低消費電力のためのサブクォ-タミクロンゲ-トCMOS/SOI回路の最適設計
Optimum Design of Subquarter-micrometer-gate CMOS/SOI Circuits for High-speed and Low-power Operation
Fujishima, Minoru
10744
University of Tokyo (東京大学)
博士(工学)
thesis
1993-03-29
1993-03-29
application/pdf
甲第09999
https://repository.dl.itc.u-tokyo.ac.jp/record/4989/files/273319.pdf
eng