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  1. 124 情報理工学系研究科
  2. 40 電子情報学専攻
  3. 1244025 修士論文(電子情報学専攻)
  1. 0 資料タイプ別
  2. 20 学位論文
  3. 025 修士論文

Implementation of Instruction Scheduler on FPGA

http://hdl.handle.net/2261/44027
301cb39c-1fc9-4208-926e-4ce866d8c0cc
名前 / ファイル ライセンス アクション
48096435.pdf 48096435.pdf (1.8 MB)
Item type 学位論文 / Thesis or Dissertation(1)
公開日 2011-08-08
タイトル
タイトル Implementation of Instruction Scheduler on FPGA
言語
言語 eng
資源タイプ
資源 http://purl.org/coar/resource_type/c_46ec
タイプ thesis
その他のタイトル
その他のタイトル FPGAへの命令・スケジューラの実装
著者 Johri, Abhishek

× Johri, Abhishek

WEKO 5274

Johri, Abhishek

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著者別名
識別子
識別子 5275
識別子Scheme WEKO
姓名
姓名 ジョーリ, アビシェク
著者所属
著者所属 東京大学大学院情報理工学系研究科電子情報学専攻
Abstract
内容記述タイプ Abstract
内容記述 This thesis describes an implementation technique of "Instruction Scheduler" on FPGA. This implementation of instruction scheduler is a part of the soft core version of an area efficient out-of-order superscalar microprocessor proposed by our lab. Instruction scheduler is a very crucial part of out-of-order microprocessor, which decides the instructions to be issued for execution. It checks for the dependencies of instructions in the instruction window and issues a certain number of instructions when their dependencies are resolved and they are ready for execution. It is a critical component of microprocessor, which limits its operational clock speed. To achieve high clock speed for the proposed FPGA implemented microprocessor, it is necessary that the instruction scheduler must achieve low data path delay on FPGA's special architecture. Hence, in this report we propose an implementation technique for instruction scheduler on FPGA, taking into account the architecture specialties and restrictions of FPGA. The proposed implementation tries to reduce the critical path delay of instruction scheduler by making intelligent use of FPGA resources. We also propose an optimization technique for Select Logic.
書誌情報 発行日 2011-03-24
日本十進分類法
主題 548
主題Scheme NDC
学位名
学位名 修士(情報理工学)
学位
値 master
研究科・専攻
情報理工学系研究科電子情報学専攻
学位授与年月日
学位授与年月日 2011-03-24
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