{"created":"2021-03-01T06:18:12.664832+00:00","id":1630,"links":{},"metadata":{"_buckets":{"deposit":"8326a986-d563-4756-8e96-d027a7c0c992"},"_deposit":{"id":"1630","owners":[],"pid":{"revision_id":0,"type":"depid","value":"1630"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00001630","sets":["34:105:262","9:233:234"]},"item_7_alternative_title_1":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"FPGAへの命令・スケジューラの実装"}]},"item_7_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2011-03-24","bibliographicIssueDateType":"Issued"},"bibliographic_titles":[{}]}]},"item_7_date_granted_25":{"attribute_name":"学位授与年月日","attribute_value_mlt":[{"subitem_dategranted":"2011-03-24"}]},"item_7_degree_name_20":{"attribute_name":"学位名","attribute_value_mlt":[{"subitem_degreename":"修士(情報理工学)"}]},"item_7_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"This thesis describes an implementation technique of \"Instruction Scheduler\" on FPGA. This implementation of instruction scheduler is a part of the soft core version of an area efficient out-of-order superscalar microprocessor proposed by our lab. Instruction scheduler is a very crucial part of out-of-order microprocessor, which decides the instructions to be issued for execution. It checks for the dependencies of instructions in the instruction window and issues a certain number of instructions when their dependencies are resolved and they are ready for execution. It is a critical component of microprocessor, which limits its operational clock speed. To achieve high clock speed for the proposed FPGA implemented microprocessor, it is necessary that the instruction scheduler must achieve low data path delay on FPGA's special architecture. Hence, in this report we propose an implementation technique for instruction scheduler on FPGA, taking into account the architecture specialties and restrictions of FPGA. The proposed implementation tries to reduce the critical path delay of instruction scheduler by making intelligent use of FPGA resources. We also propose an optimization technique for Select Logic.","subitem_description_type":"Abstract"}]},"item_7_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"5275","nameIdentifierScheme":"WEKO"}],"names":[{"name":"ジョーリ, アビシェク"}]}]},"item_7_select_21":{"attribute_name":"学位","attribute_value_mlt":[{"subitem_select_item":"master"}]},"item_7_subject_13":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"548","subitem_subject_scheme":"NDC"}]},"item_7_text_24":{"attribute_name":"研究科・専攻","attribute_value_mlt":[{"subitem_text_value":"情報理工学系研究科電子情報学専攻"}]},"item_7_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院情報理工学系研究科電子情報学専攻"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Johri, Abhishek"}],"nameIdentifiers":[{"nameIdentifier":"5274","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-05-31"}],"displaytype":"detail","filename":"48096435.pdf","filesize":[{"value":"1.8 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"48096435.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/1630/files/48096435.pdf"},"version_id":"ebf263c0-2d6f-434a-b35c-3cbea7d8e1ec"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"thesis","resourceuri":"http://purl.org/coar/resource_type/c_46ec"}]},"item_title":"Implementation of Instruction Scheduler on FPGA","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Implementation of Instruction Scheduler on FPGA"}]},"item_type_id":"7","owner":"1","path":["234","262"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-08-08"},"publish_date":"2011-08-08","publish_status":"0","recid":"1630","relation_version_is_last":true,"title":["Implementation of Instruction Scheduler on FPGA"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:43:00.525067+00:00"}