{"created":"2021-03-01T06:18:23.097388+00:00","id":1797,"links":{},"metadata":{"_buckets":{"deposit":"87ad7158-f0e3-47a2-b0fa-8b83affbe37e"},"_deposit":{"id":"1797","owners":[],"pid":{"revision_id":0,"type":"depid","value":"1797"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00001797","sets":["6:260:261","9:233:234"]},"item_7_alternative_title_1":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"Modeling and Optimization of On-Chip Transmission Line"}]},"item_7_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2006-02-03","bibliographicIssueDateType":"Issued"},"bibliographic_titles":[{}]}]},"item_7_date_granted_25":{"attribute_name":"学位授与年月日","attribute_value_mlt":[{"subitem_dategranted":"2006-03-23"}]},"item_7_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"RF-CMOS回路において、低損失の伝送線路を実現可能なスローウェーブ伝送線路(SWTL)構造を提案し、その最適化に必要となるレイアウト及び周波数に依存したモデルを作成した。また、伝送線路中を伝播する信号の波長を短くすることで、実装線路長を短縮し、回路面積を削減できるため、線路中の波長を短縮するオンチップ伝送線路構造を提案した。","subitem_description_type":"Abstract"}]},"item_7_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"5589","nameIdentifierScheme":"WEKO"}],"names":[{"name":"Tanimoto, Hideyuki"}]}]},"item_7_select_21":{"attribute_name":"学位","attribute_value_mlt":[{"subitem_select_item":"master"}]},"item_7_subject_13":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549","subitem_subject_scheme":"NDC"}]},"item_7_text_24":{"attribute_name":"研究科・専攻","attribute_value_mlt":[{"subitem_text_value":"工学系研究科電子工学専攻"}]},"item_7_text_27":{"attribute_name":"学位記番号","attribute_value_mlt":[{"subitem_text_value":"修第号"}]},"item_7_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科 電子工学専攻"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"谷本, 英之"}],"nameIdentifiers":[{"nameIdentifier":"5588","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-05-31"}],"displaytype":"detail","filename":"tanimoto.pdf","filesize":[{"value":"2.0 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"tanimoto.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/1797/files/tanimoto.pdf"},"version_id":"3c9e86f7-3373-4020-a26c-2c8681d0a799"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"伝送線路","subitem_subject_scheme":"Other"},{"subitem_subject":"Transmission Line","subitem_subject_scheme":"Other"},{"subitem_subject":"RF-CMOS","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"jpn"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"thesis","resourceuri":"http://purl.org/coar/resource_type/c_46ec"}]},"item_title":"オンチップ伝送線路のモデリングと最適化","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"オンチップ伝送線路のモデリングと最適化"}]},"item_type_id":"7","owner":"1","path":["234","261"],"pubdate":{"attribute_name":"公開日","attribute_value":"2011-08-08"},"publish_date":"2011-08-08","publish_status":"0","recid":"1797","relation_version_is_last":true,"title":["オンチップ伝送線路のモデリングと最適化"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:43:13.605425+00:00"}