{"created":"2021-03-01T06:16:43.365696+00:00","id":188,"links":{},"metadata":{"_buckets":{"deposit":"192a4eac-827f-4316-b442-bd07b91b4f9d"},"_deposit":{"id":"188","owners":[],"pid":{"revision_id":0,"type":"depid","value":"188"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00000188","sets":["75:76:77","9:10:14"]},"item_2_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2008-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"3","bibliographicPageEnd":"1637","bibliographicPageStart":"1631","bibliographicVolumeNumber":"55","bibliographic_titles":[{"bibliographic_title":"IEEE transactions on nuclear science"}]}]},"item_2_description_13":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Transmission Control Protocol (TCP) and Ethernet have been widely used in readout systems. These protocols are defacto standards and have been implemented on standard operating systems. However, some small devices, e.g., front-end devices and detectors, are not capable of employing these protocols because of hardware size limitations. This paper describes a TCP processor for Gigabit Ethernet with a circuit size suitable for implementing on a single field programmable gate array. The only peripheral device required is a single Ethernet physical layer device. The hardware was implemented and its TCP throughput was measured. The throughputs in both directions simultaneously were at the upper limits of Gigabit Ethernet. A mechanism for slow control over User Datagram Protocol (UDP) is also provided. The processor described here allows adoption of TCP/Ethernet in small devices that have hardware size limitations.","subitem_description_type":"Abstract"}]},"item_2_publisher_20":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE"}]},"item_2_relation_11":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"info:doi/10.1109/TNS.2008.920264","subitem_relation_type_select":"DOI"}}]},"item_2_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"©2008 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]},"item_2_select_14":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_select_item":"publisher"}]},"item_2_source_id_10":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00667999","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"00189499","subitem_source_identifier_type":"ISSN"}]},"item_2_subject_15":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"539","subitem_subject_scheme":"NDC"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Uchida, Tomohisa"}],"nameIdentifiers":[{"nameIdentifier":"105963","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-06-26"}],"displaytype":"detail","filename":"uchida_tns55.pdf","filesize":[{"value":"661.3 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"uchida_tns55.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/188/files/uchida_tns55.pdf"},"version_id":"9263bd48-ab25-461c-bba9-c0a907d6f2c9"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Ethernet","subitem_subject_scheme":"Other"},{"subitem_subject":"FPGA","subitem_subject_scheme":"Other"},{"subitem_subject":"TCP/IP","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Hardware-Based TCP Processor for Gigabit Ethernet","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Hardware-Based TCP Processor for Gigabit Ethernet"}]},"item_type_id":"2","owner":"1","path":["14","77"],"pubdate":{"attribute_name":"公開日","attribute_value":"2008-06-23"},"publish_date":"2008-06-23","publish_status":"0","recid":"188","relation_version_is_last":true,"title":["Hardware-Based TCP Processor for Gigabit Ethernet"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:41:08.464587+00:00"}