{"created":"2021-03-01T06:16:33.481788+00:00","id":23,"links":{},"metadata":{"_buckets":{"deposit":"0188032f-1b13-4402-8d3f-ea4c62d14cee"},"_deposit":{"id":"23","owners":[],"pid":{"revision_id":0,"type":"depid","value":"23"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00000023","sets":["12:13","9:10:14"]},"item_2_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2001-03","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"1","bibliographicPageEnd":"973","bibliographicPageStart":"970","bibliographicVolumeNumber":"11","bibliographic_titles":[{"bibliographic_title":"IEEE transactions on applied superconductivity : a publication of the IEEE Superconductivity Committee"}]}]},"item_2_description_13":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Recently we have proposed novel Boolean Single-Flux-quantum (BSFQ) circuits, which Just like CMOS circuits support Boolean primitives directly, and do not require local synchronization for each operation cell. However, previous BSFQ AND, OR, and XOR cells suffered from problems with narrow margin, where their critical margins hardly exceeded +/- 10% due to low flux gain. Furthermore, while being suitable for combinational circuits, previous BSFQ NOT cells had initialization problems in sequential circuits. In this paper, new versions of these circuits with simulated margins beyond +/- 30% are proposed. Moreover, a Muller C-element, an error canceller, a destructive read-out (DRO), and a demultiplexer are also newly created. The operation time, parameter margins, and circuit size of these BSFQ cells are comparable to those of the conventional RSFQ cells.","subitem_description_type":"Abstract"}]},"item_2_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"97","nameIdentifierScheme":"WEKO"}],"names":[{"name":"岡部, 洋一"}]}]},"item_2_publisher_20":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC"}]},"item_2_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"©2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]},"item_2_source_id_10":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10791666","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"10518223","subitem_source_identifier_type":"ISSN"}]},"item_2_subject_15":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549.3","subitem_subject_scheme":"NDC"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Teh, CK"}],"nameIdentifiers":[{"nameIdentifier":"95","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Okabe, Yoichi"}],"nameIdentifiers":[{"nameIdentifier":"96","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-05-30"}],"displaytype":"detail","filename":"IEEE_A_S_2001_11_1_970.pdf","filesize":[{"value":"496.3 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"IEEE_A_S_2001_11_1_970.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/23/files/IEEE_A_S_2001_11_1_970.pdf"},"version_id":"cce0f8aa-3799-4cc0-8ebf-0fe46afd27ff"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"asynchronous circuits","subitem_subject_scheme":"Other"},{"subitem_subject":"BSFQ","subitem_subject_scheme":"Other"},{"subitem_subject":"Boolean primitives","subitem_subject_scheme":"Other"},{"subitem_subject":"dual-rail","subitem_subject_scheme":"Other"},{"subitem_subject":"flux level","subitem_subject_scheme":"Other"},{"subitem_subject":"level logic","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"New BSFQ circuit designs with wide margins","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"New BSFQ circuit designs with wide margins"}]},"item_type_id":"2","owner":"1","path":["13","14"],"pubdate":{"attribute_name":"公開日","attribute_value":"2006-02-13"},"publish_date":"2006-02-13","publish_status":"0","recid":"23","relation_version_is_last":true,"title":["New BSFQ circuit designs with wide margins"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:40:55.432955+00:00"}