{"created":"2021-03-01T06:16:33.541970+00:00","id":24,"links":{},"metadata":{"_buckets":{"deposit":"c4855ab1-88c9-43fb-88ff-ab886d2a6527"},"_deposit":{"id":"24","owners":[],"pid":{"revision_id":0,"type":"depid","value":"24"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00000024","sets":["12:13","9:10:14"]},"item_2_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1999-06","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicPageEnd":"3732","bibliographicPageStart":"3729","bibliographicVolumeNumber":"9","bibliographic_titles":[{"bibliographic_title":"IEEE transactions on applied superconductivity : a publication of the IEEE Superconductivity Committee"}]}]},"item_2_description_13":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_description":"application/pdf","subitem_description_type":"Other"}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"We propose a new class of SFQ logic circuits. In this new approach, an SFQ pulse represents the transition between \"zero\" and \"one\". By using these two bits of information, a one-to-one correspondence between input and output can be realized. Since the correspondence is then the same as in semiconductor circuits, this method permits logic design without clock elements. In order to carry out this logic, we propose the most fundamental element, a new DC/SFQ converter. A computer simulation and low-speed test were performed. Both results showed that this converter operates correctly with a wide margin. Moreover, this converter also pro, ides the basis for many other logic elements such as AND, OR, and XOR.","subitem_description_type":"Abstract"}]},"item_2_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"102","nameIdentifierScheme":"WEKO"}],"names":[{"name":"岡部, 洋一"}]}]},"item_2_publisher_20":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC"}]},"item_2_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"©1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]},"item_2_source_id_10":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA10791666","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"10518223","subitem_source_identifier_type":"ISSN"}]},"item_2_subject_15":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549.37","subitem_subject_scheme":"NDC"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kodaka, Hiroki"}],"nameIdentifiers":[{"nameIdentifier":"98","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Hosoki, Tetsu"}],"nameIdentifiers":[{"nameIdentifier":"99","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Kitagawa, Manabu"}],"nameIdentifiers":[{"nameIdentifier":"100","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Okabe, Yoichi"}],"nameIdentifiers":[{"nameIdentifier":"101","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-05-30"}],"displaytype":"detail","filename":"IEEE_A_S_1999_9_2_3_3729.pdf","filesize":[{"value":"507.7 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"IEEE_A_S_1999_9_2_3_3729.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/24/files/IEEE_A_S_1999_9_2_3_3729.pdf"},"version_id":"7b91106b-0354-40af-9abb-20700e20eb66"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"SFQ data processing with set/reset information","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"SFQ data processing with set/reset information"}]},"item_type_id":"2","owner":"1","path":["13","14"],"pubdate":{"attribute_name":"公開日","attribute_value":"2006-02-13"},"publish_date":"2006-02-13","publish_status":"0","recid":"24","relation_version_is_last":true,"title":["SFQ data processing with set/reset information"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:40:57.091659+00:00"}