{"created":"2021-03-01T06:19:24.448166+00:00","id":2791,"links":{},"metadata":{"_buckets":{"deposit":"c4b2ecbd-9681-41f0-b42a-ebe022a72ca0"},"_deposit":{"id":"2791","owners":[],"pid":{"revision_id":0,"type":"depid","value":"2791"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00002791","sets":["6:260:318","9:233:280"]},"item_7_alternative_title_1":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"設計固有セルライブラリの最適生成手法"}]},"item_7_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2007-03-22","bibliographicIssueDateType":"Issued"},"bibliographic_titles":[{}]}]},"item_7_date_granted_25":{"attribute_name":"学位授与年月日","attribute_value_mlt":[{"subitem_dategranted":"2007-03-22"}]},"item_7_degree_grantor_23":{"attribute_name":"学位授与機関","attribute_value_mlt":[{"subitem_degreegrantor":[{"subitem_degreegrantor_name":"University of Tokyo (東京大学)"}]}]},"item_7_degree_name_20":{"attribute_name":"学位名","attribute_value_mlt":[{"subitem_degreename":"博士(工学)"}]},"item_7_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"This dissertation focuses on optimal generation of design-specific cell libraries. In cell-based integrated circuit design, a cell library defines the final quality of a design. Hence, use of a general-purpose cell library may lead to a poor quality. We address various issues regarding optimal generation of design-specific cell libraries, targeting high-performance digital circuit design. The goal of the first part of the dissertation is to provide the key components required to successfully realize the automatic generation of design-specific cell libraries, which consists of cell logic type selection and drive strength type selection. Chapter 2 addresses feasibility issues on transistor-level optimization. During transistor-level optimization, cell layout synthesis and characterization steps are the major bottlenecks with respect to runtime. To resolve this drawback, we present a fast and accurate prelayout estimation technique of cell characteristics. Our estimation technique is based on quick transistor placement. Given a transistor-level circuit of a cell, layout parasitics are estimated using quick transistor placement. Then, the cell is characterized by simulating an estimated circuit which is built according to the estimated layout parasitics. Experimental results on a 0.13um industrial standard cell library demonstrate that the proposed technique estimates the cell characteristics with a reasonable accuracy in a negligibly small amount of time. Chapter 3 addresses a cell logic type selection problem for design-specific cell libraries. Our methodology consists of two steps: logic-rich cell library generation and cell logic type count minimization. We propose a cell logic type count minimization method which minimizes the logic type count iteratively under performance constraints. Experimental results on the ISCAS 85 benchmark suite in an industrial 90nm technology demonstrate that it is feasible to find the minimal set of cell logic types under performance constraints. Chapter 4 addresses a performance-constrained cell count minimization problem for continuously-sized circuits. After providing a formal formulation of the problem, we propose an effective heuristic for the problem. The proposed hill-climbing heuristic iteratively minimizes the number of cells under performance constraints such as area, delay and power. Experimental results on the ISCAS 85 benchmark suite in an industrial 90nm technology demonstrate its effectiveness. We also discuss several implementation issues towards a practical application of the proposed method to large-scale circuits. The second part of the dissertation focuses on transistor-level topology synthesis, which is an important component in the manual generation phase where portions of a circuit are manually identified and cells for the portions are synthesized at the transistor level. We present three transistor-level topology synthesis methods. Although their objectives are to minimize the transistor count, they have different solution spaces. Combining these methods, the minimum solution in larger solution space can be obtained. Chapter 5 presents a method for synthesis of minimal static CMOS circuits where the solution space is restricted to the circuit structures which can be obtained by performing algebraic transformations on an arbitrary prime-and-irredundant two-level circuit. The circuit structures are implicitly enumerated via structural transformations on a single graph structure, then a dynamic-programming based algorithm efficiently finds the minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations demonstrate the feasibility of the proposed procedure. We also demonstrate the efficiency of the proposed algorithm by a numerical analysis on randomly-generated problems. It is also shown that the proposed procedure sometimes generates significantly smaller circuits compared to conventional approach. Chapter 6 presents an exact method for minimum logic factoring which can be viewed as the synthesis of a static CMOS compound gate. We first introduce a novel graph structure, called an X-B (eXchanger Binary) tree, which implicitly enumerates binary trees. Using this X-B tree, the factoring problem is compactly transformed into a quantified Boolean formula (QBF) and is solved by general-purpose QBF solver. Experimental results on artificially-created benchmark functions show that the proposed method successfully finds the exact minimum solutions to the problems with up to 12 literals. Chapter 7 studies the synthesis of read-once switch networks in which every variable appears only once. The proposed procedure is based on the notions of prime implicants and unateness, which establish a basis for Boolean expression synthesis. We also propose a pruning technique for an efficient search. Experimental results on randomly-generated problems with up to 20 switches demonstrate that the proposed procedure successfully solves about 90% of the problems in 10 minutes each and the resulting read-once switch networks are up to 78% smaller compared to series-parallel switch networks. Chapter 8 conducts an experimental study using a circuit consisting of C432 and C499 from the ISCAS 85 benchmark suite as a design example. We compare the circuits synthesized with a typical cell library and optimal design-specific libraries in an industrial 90nm technology, and demonstrate that using the design-specific cell libraries, the area-delay tradeoff curve is shifted to the left-bottom from that using the typical library. Comparing between the area-optimal circuits, the area is improved by 27.3%. And, comparing between the delay-optimal circuits, the maximum delay is improved by 22.4%. These results clearly prove the effectiveness of the flow and the key components for optimal generation of design-specific cell libraries.","subitem_description_type":"Abstract"}]},"item_7_dissertation_number_26":{"attribute_name":"学位授与番号","attribute_value_mlt":[{"subitem_dissertationnumber":"甲第22279号"}]},"item_7_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"7354","nameIdentifierScheme":"WEKO"}],"names":[{"name":"吉田, 浩章"}]}]},"item_7_identifier_registration":{"attribute_name":"ID登録","attribute_value_mlt":[{"subitem_identifier_reg_text":"10.15083/00002785","subitem_identifier_reg_type":"JaLC"}]},"item_7_select_21":{"attribute_name":"学位","attribute_value_mlt":[{"subitem_select_item":"doctoral"}]},"item_7_subject_13":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549","subitem_subject_scheme":"NDC"}]},"item_7_text_22":{"attribute_name":"学位分野","attribute_value_mlt":[{"subitem_text_value":"Engineering (工学)"}]},"item_7_text_24":{"attribute_name":"研究科・専攻","attribute_value_mlt":[{"subitem_text_value":"Department of Electronic Engineering, Graduate School of Engineering (工学系研究科電子工学専攻)"}]},"item_7_text_27":{"attribute_name":"学位記番号","attribute_value_mlt":[{"subitem_text_value":"博工第6484号"}]},"item_7_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科電子工学専攻"},{"subitem_text_value":"Department of Electronic Engineering, Graduate School of Engineering, The University of Tokyo"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yoshida, Hiroaki"}],"nameIdentifiers":[{"nameIdentifier":"7353","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-05-31"}],"displaytype":"detail","filename":"K-122279.pdf","filesize":[{"value":"9.6 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"K-122279.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/2791/files/K-122279.pdf"},"version_id":"6d081271-b27b-402c-9503-6407f5338892"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"thesis","resourceuri":"http://purl.org/coar/resource_type/c_46ec"}]},"item_title":"Optimal Generation of Design-Specific Cell Libraries","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Optimal Generation of Design-Specific Cell Libraries"}]},"item_type_id":"7","owner":"1","path":["280","318"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-03-01"},"publish_date":"2012-03-01","publish_status":"0","recid":"2791","relation_version_is_last":true,"title":["Optimal Generation of Design-Specific Cell Libraries"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:44:42.333651+00:00"}