{"created":"2021-03-01T06:17:11.989103+00:00","id":656,"links":{},"metadata":{"_buckets":{"deposit":"c4e8b576-4f02-4ec5-aebb-5ac294ddbb35"},"_deposit":{"id":"656","owners":[],"pid":{"revision_id":0,"type":"depid","value":"656"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00000656","sets":["12:13","9:10:14"]},"item_2_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"1985-05","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"2","bibliographicPageEnd":"581","bibliographicPageStart":"578","bibliographicVolumeNumber":"21","bibliographic_titles":[{"bibliographic_title":"IEEE transactions on magnetics"}]}]},"item_2_description_5":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible.","subitem_description_type":"Abstract"}]},"item_2_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"2170","nameIdentifierScheme":"WEKO"}],"names":[{"name":"岡部, 洋一"}]}]},"item_2_publisher_20":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC"}]},"item_2_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"©1985 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]},"item_2_source_id_10":{"attribute_name":"書誌レコードID","attribute_value_mlt":[{"subitem_source_identifier":"AA00667933","subitem_source_identifier_type":"NCID"}]},"item_2_source_id_8":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"00189464","subitem_source_identifier_type":"ISSN"}]},"item_2_subject_15":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549.2","subitem_subject_scheme":"NDC"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Miyake, H"}],"nameIdentifiers":[{"nameIdentifier":"2166","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Fukaya, N"}],"nameIdentifiers":[{"nameIdentifier":"2167","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Okabe, Yoichi"}],"nameIdentifiers":[{"nameIdentifier":"2168","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Sugano, T"}],"nameIdentifiers":[{"nameIdentifier":"2169","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-05-30"}],"displaytype":"detail","filename":"IEEE_M_1985_21_2_578.pdf","filesize":[{"value":"427.0 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"IEEE_M_1985_21_2_578.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/656/files/IEEE_M_1985_21_2_578.pdf"},"version_id":"957bb87c-56ef-463d-8e4c-898157f5d5e2"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"PROPOSAL OF UNILATERAL SINGLE-FLUX-QUANTUM LOGIC GATE","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"PROPOSAL OF UNILATERAL SINGLE-FLUX-QUANTUM LOGIC GATE"}]},"item_type_id":"2","owner":"1","path":["13","14"],"pubdate":{"attribute_name":"公開日","attribute_value":"2015-02-04"},"publish_date":"2015-02-04","publish_status":"0","recid":"656","relation_version_is_last":true,"title":["PROPOSAL OF UNILATERAL SINGLE-FLUX-QUANTUM LOGIC GATE"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:41:36.235186+00:00"}