{"created":"2021-03-01T06:25:39.767986+00:00","id":8836,"links":{},"metadata":{"_buckets":{"deposit":"dd7eb28a-c1eb-4398-87c8-a85eeaa95666"},"_deposit":{"id":"8836","owners":[],"pid":{"revision_id":0,"type":"depid","value":"8836"},"status":"published"},"_oai":{"id":"oai:repository.dl.itc.u-tokyo.ac.jp:00008836","sets":["6:260:318","9:233:280"]},"item_7_alternative_title_1":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"２線式しきい値論理回路を用いた配列型CMOS論理アーキテクチャに関する研究"}]},"item_7_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2004-03-25","bibliographicIssueDateType":"Issued"},"bibliographic_titles":[{}]}]},"item_7_date_granted_25":{"attribute_name":"学位授与年月日","attribute_value_mlt":[{"subitem_dategranted":"2004-03-25"}]},"item_7_degree_grantor_23":{"attribute_name":"学位授与機関","attribute_value_mlt":[{"subitem_degreegrantor":[{"subitem_degreegrantor_name":"University of Tokyo (東京大学)"}]}]},"item_7_degree_name_20":{"attribute_name":"学位名","attribute_value_mlt":[{"subitem_degreename":"博士(工学)"}]},"item_7_dissertation_number_26":{"attribute_name":"学位授与番号","attribute_value_mlt":[{"subitem_dissertationnumber":"甲第19025号"}]},"item_7_full_name_3":{"attribute_name":"著者別名","attribute_value_mlt":[{"nameIdentifiers":[{"nameIdentifier":"17837","nameIdentifierScheme":"WEKO"}],"names":[{"name":"山岡, 寛明"}]}]},"item_7_identifier_registration":{"attribute_name":"ID登録","attribute_value_mlt":[{"subitem_identifier_reg_text":"10.15083/00008827","subitem_identifier_reg_type":"JaLC"}]},"item_7_select_21":{"attribute_name":"学位","attribute_value_mlt":[{"subitem_select_item":"doctoral"}]},"item_7_subject_13":{"attribute_name":"日本十進分類法","attribute_value_mlt":[{"subitem_subject":"549.7","subitem_subject_scheme":"NDC"}]},"item_7_text_22":{"attribute_name":"学位分野","attribute_value_mlt":[{"subitem_text_value":"Engineering (工学)"}]},"item_7_text_24":{"attribute_name":"研究科・専攻","attribute_value_mlt":[{"subitem_text_value":"Department of Electronic Engineering, Graduate School of Engineering (工学系研究科電子工学専攻)"}]},"item_7_text_27":{"attribute_name":"学位記番号","attribute_value_mlt":[{"subitem_text_value":"博工第5757号"}]},"item_7_text_4":{"attribute_name":"著者所属","attribute_value_mlt":[{"subitem_text_value":"東京大学大学院工学系研究科 電子工学専攻"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Yamaoka, Akihiro"}],"nameIdentifiers":[{"nameIdentifier":"17836","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2017-06-05"}],"displaytype":"detail","filename":"119025.pdf","filesize":[{"value":"12.4 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"119025.pdf","url":"https://repository.dl.itc.u-tokyo.ac.jp/record/8836/files/119025.pdf"},"version_id":"799a8f45-97a8-452f-b7aa-06f484167e30"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"集積回路","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"thesis","resourceuri":"http://purl.org/coar/resource_type/c_46ec"}]},"item_title":"CMOS Array Logic Architectures Using Dual-Rail Threshold Logic Circuits","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"CMOS Array Logic Architectures Using Dual-Rail Threshold Logic Circuits"}]},"item_type_id":"7","owner":"1","path":["280","318"],"pubdate":{"attribute_name":"公開日","attribute_value":"2017-01-13"},"publish_date":"2017-01-13","publish_status":"0","recid":"8836","relation_version_is_last":true,"title":["CMOS Array Logic Architectures Using Dual-Rail Threshold Logic Circuits"],"weko_creator_id":"1","weko_shared_id":null},"updated":"2022-12-19T03:52:43.418794+00:00"}