WEKO3
アイテム
New BSFQ circuit designs with wide margins
http://hdl.handle.net/2261/35
http://hdl.handle.net/2261/35e245b21b-42f5-4a55-9742-38b621342f0b
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IEEE_A_S_2001_11_1_970.pdf (496.3 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2006-02-13 | |||||
| タイトル | ||||||
| タイトル | New BSFQ circuit designs with wide margins | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | asynchronous circuits | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | BSFQ | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Boolean primitives | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | dual-rail | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | flux level | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | level logic | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 著者 |
Teh, CK
× Teh, CK× Okabe, Yoichi |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 97 | |||||
| 姓名 | 岡部, 洋一 | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Recently we have proposed novel Boolean Single-Flux-quantum (BSFQ) circuits, which Just like CMOS circuits support Boolean primitives directly, and do not require local synchronization for each operation cell. However, previous BSFQ AND, OR, and XOR cells suffered from problems with narrow margin, where their critical margins hardly exceeded +/- 10% due to low flux gain. Furthermore, while being suitable for combinational circuits, previous BSFQ NOT cells had initialization problems in sequential circuits. In this paper, new versions of these circuits with simulated margins beyond +/- 30% are proposed. Moreover, a Muller C-element, an error canceller, a destructive read-out (DRO), and a demultiplexer are also newly created. The operation time, parameter margins, and circuit size of these BSFQ cells are comparable to those of the conventional RSFQ cells. | |||||
| 書誌情報 |
IEEE transactions on applied superconductivity : a publication of the IEEE Superconductivity Committee 巻 11, 号 1, p. 970-973, 発行日 2001-03 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 10518223 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA10791666 | |||||
| 権利 | ||||||
| 権利情報 | ©2001 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
| フォーマット | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | application/pdf | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 549.3 | |||||
| 出版者 | ||||||
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |||||
