WEKO3
アイテム
Low-overhead security-tagged architecture
http://hdl.handle.net/2261/28045
http://hdl.handle.net/2261/28045cd58b4d0-0cbf-46e6-a043-26742be7fdc8
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
kim.pdf (856.2 kB)
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| Item type | 学位論文 / Thesis or Dissertation(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2011-08-08 | |||||
| タイトル | ||||||
| タイトル | Low-overhead security-tagged architecture | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_46ec | |||||
| タイプ | thesis | |||||
| その他のタイトル | ||||||
| その他のタイトル | 低オーバヘッド セキュリティ・タグ・アーキテクチャ | |||||
| 著者 |
Kim, Daewung
× Kim, Daewung |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 5658 | |||||
| 姓名 | 金, 大雄 | |||||
| 著者所属 | ||||||
| 著者所属 | 情報理工学系研究科 電子情報学専攻 | |||||
| Abstract | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | A tagged architecture is a system that applies tags on data, recently used in the field of information security./ The previous studies using tagged architecture mostly focused on how to utilize tags, not how the tags are implemented. A naive implementation of tags simply adds a tag field to every byte of the cache and the memory. Such technique, however, results in a huge hardware overhead and performance degradation, as well as is unable to support variable-length tags./ This thesis proposes a low-overhead security-tagged architecture that supports variable-length tags. We achieve our goal by separating tag and data completely. The proposal technique is composed of two parts, separation in storage and separation in execution./ First, in the separation of storage, we exploiting some properties of tag, the non-uniformity and the locality of reference. Our design includes a use of uniquely designed multi-level table and various cache-like structures, all contributing to exploit these properties./ Second, in the separation of execution, we suggest to propagate tags after the completion of execution of data. This allows to have dedicated tag register file and L1 tag cache, so that prevent to increase in the access latency for register and cache. Under simulation, our method was able to reduce the memory overhead to 3.48% of the naive implementation, and 4.96% of IPC degradation compared with conventional computer system, in addition to supporting variable-length tag. | |||||
| 書誌情報 | 発行日 2009-03-23 | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 548 | |||||
| 学位名 | ||||||
| 学位名 | 修士(情報理工学) | |||||
| 学位 | ||||||
| 値 | master | |||||
| 研究科・専攻 | ||||||
| 情報理工学系研究科電子情報学専攻 | ||||||
| 学位授与年月日 | ||||||
| 学位授与年月日 | 2009-03-23 | |||||
