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Study on Applications of Room-Temperature Operating Silicon Single-Electron Transistors
https://doi.org/10.15083/00002421
https://doi.org/10.15083/00002421ed00d39e-c518-433f-a420-dd26103584c2
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
37057080.pdf (1.0 MB)
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| Item type | 学位論文 / Thesis or Dissertation(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2012-03-01 | |||||
| タイトル | ||||||
| タイトル | Study on Applications of Room-Temperature Operating Silicon Single-Electron Transistors | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | silicon | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | single-electron transistor | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | room temperature | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Coulomb blockade | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_46ec | |||||
| タイプ | thesis | |||||
| ID登録 | ||||||
| ID登録 | 10.15083/00002421 | |||||
| ID登録タイプ | JaLC | |||||
| その他のタイトル | ||||||
| その他のタイトル | 室温動作シリコン単電子トランジスタとその応用 | |||||
| 著者 |
Miyaji, Kousuke
× Miyaji, Kousuke |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 6690 | |||||
| 姓名 | 宮地, 幸祐 | |||||
| 著者所属 | ||||||
| 著者所属 | 東京大学大学院工学系研究科 電子工学専攻 | |||||
| Abstract | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | For the past 30 years, the size of a metal-oxide-semiconductor field-effect-transistor (MOSFET) in very-large-scale integrated circuits (VLSI) continued to scale down for higher integration and higher performance. As the gate length of MOSFETs has reached down to sub-50 nm, unprecedented technical issues have become prominent to proceed scaling of the MOSFETs. Silicon single-electron transistor/single-hole transistor (SET/SHT) is one of the most promising devices for VLSI in silicon nanotechnology; the technology that seeks new function in nano structures. Although its operation principle is different from conventional MOSFETs, its fabrication process is very similar to them. Hence, it is expected that SETs/SHTs can be easily combined with CMOS VLSI and realize high functional, ultra-low power, and ultra-high density circuits. Owing to the intensive researches on SETs/SHTs, process techniques for SETs/SHTs to operate at room temperature have been establishes. In such room-temperature operating SETs/SHTs, strong quantum effect has become pronounced and started to affect the transport characteristics. However, basic analysis and enhancement of the device performance are still required for room-temperature-operating SETs/SHTs to be used in actual VLSI circuits. The objective of this work is to analyze the characteristics of the room-temperature-operating SETs/SHTs and apply them to further enhance their advantages for VLSI circuit applications. The feasibilities of the proposed methods are evaluated by simulations and measurements. An analytical SET/SHT model with discrete quantum energy levels has been proposed and developed. The model is compact enough to be expressed in closed-form, thus it does not require numerical calculation. As discrete quantum levels are introduced, it can successfully reproduce NDC characteristics and non-periodic Coulomb oscillations. The model is accurate compared to the conventional full master equation method and the measured data. Also, the model can be incorporated into the HSPICE simulation. The proposed analytical model is promising to provide suitable environments for designing CMOS-combined room-temperature- operating highly-functional SET circuits. The relationship between the FWHM of the NDC and voltage gain has been newly found by the experiments and calculations. The high gain SETs/SHTs show small FWHM in NDC. Therefore, NDC characteristics can be controlled by the basic capacitance parameters. Low drain coupling in the high gain SETs/SHTs is considered to be the most possible origin. High-gain SETs/SHTs can realize low supply voltage in NDC circuits while they still have advantages in the standard logic circuits. Sharpness (FWHM) of Coulomb blockade oscillation peak has been electrically modulated in a SHT at room temperature to enhance the functionality of the present SETs/SHTs after the device fabrication. In order to achieve the function, substrate capacitance is changed by controlling the substrate condition between depletion and accumulation (inversion) in a thin BOX SOI substrate. The proposed scheme can be applied to the novel analog pattern matching device. | |||||
| 書誌情報 | 発行日 2008-03-24 | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 549 | |||||
| 学位名 | ||||||
| 学位名 | 博士(工学) | |||||
| 学位 | ||||||
| 値 | doctoral | |||||
| 学位分野 | ||||||
| Engineering (工学) | ||||||
| 学位授与機関 | ||||||
| 学位授与機関名 | University of Tokyo (東京大学) | |||||
| 研究科・専攻 | ||||||
| Department of Electronic Engineering, Graduate School of Engineering (工学系研究科電子工学専攻) | ||||||
| 学位授与年月日 | ||||||
| 学位授与年月日 | 2008-03-24 | |||||
| 学位授与番号 | ||||||
| 学位授与番号 | 甲第23452号 | |||||
| 学位記番号 | ||||||
| 博工第6768号 | ||||||
