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  1. 124 情報理工学系研究科
  2. 40 電子情報学専攻
  3. 1244025 修士論文(電子情報学専攻)
  1. 0 資料タイプ別
  2. 20 学位論文
  3. 025 修士論文

Switch-on-Future-Event : A New Multithreaded Architecture for Single Programs

http://hdl.handle.net/2261/51729
http://hdl.handle.net/2261/51729
dfd8802f-196e-449e-be8f-6460d07bf3ba
名前 / ファイル ライセンス アクション
48106410.pdf 48106410.pdf (735.7 kB)
Item type 学位論文 / Thesis or Dissertation(1)
公開日 2012-05-29
タイトル
タイトル Switch-on-Future-Event : A New Multithreaded Architecture for Single Programs
言語
言語 eng
資源タイプ
資源 http://purl.org/coar/resource_type/c_46ec
タイプ thesis
その他のタイトル
その他のタイトル Switch-on-Future-Event : 単一プログラムを高速化する新しいマルチスレッドアーキテクチャ
著者 Kurata, Naruki

× Kurata, Naruki

WEKO 8184

Kurata, Naruki

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著者別名
識別子Scheme WEKO
識別子 8185
姓名 倉田, 成己
著者所属
著者所属 東京大学大学院情報理工学系研究科電子情報学専攻
著者所属
著者所属 Department of Information and Communication Engineering, Graduate School of Information Science and Technology, The University of Tokyo
Abstract
内容記述タイプ Abstract
内容記述 Delinquent instructions are a small number of static instructions that cause most branch prediction misses and cache misses in a program. These delinquent instructions are one of the main factors that degrade the performance of recent processors. One multithreading scheme that hides the latency of such delinquent instructions and speed up a single program is called Helper Threading. Helper Threading creates a helper thread which consists of a delinquent instruction and the instructions it depends on, and executes them earlier than the main thread to achieve accurate branch prediction or prefetching. However, we found an important feature of the delinquent instructions that most of them are executed in small loops. In such a small loop, Helper Threading cannot improve performance because it not only cannot do pre-execution sufficiently earlier than the main thread, but also prevents it from executing. We propose a new scheme of multithreading called Switch-on-Future-Event Multithreading (SoF-MT). SoF-MT regards each iteration of a loop as a thread and executes them simultaneously. The processor switches a thread when it fetches a delinquent instruction to hide the latency of a miss that the instruction will cause in the future. This technique works well because delinquent instructions are in small loops and the processor can create a sufficient number of threads to switch. This scheme is free from the problems which Helper Threading suffers from. Simulation results show that our proposal achieves performance improvement by an average of 10.1% and a maximum of 38.7%, whereas Helper Threading provides only 13.2% speedup at a maximum.
書誌情報 発行日 2012-03-22
日本十進分類法
主題Scheme NDC
主題 007
学位名
学位名 修士(情報理工学)
学位
値 master
研究科・専攻
情報理工学系研究科電子情報学専攻
学位授与年月日
学位授与年月日 2012-03-22
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