WEKO3
アイテム
SFQ data processing with set/reset information
http://hdl.handle.net/2261/36
http://hdl.handle.net/2261/3628d7370b-12d3-48ca-b9ec-2a27c0eed5ea
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IEEE_A_S_1999_9_2_3_3729.pdf (507.7 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2006-02-13 | |||||
| タイトル | ||||||
| タイトル | SFQ data processing with set/reset information | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 著者 |
Kodaka, Hiroki
× Kodaka, Hiroki× Hosoki, Tetsu× Kitagawa, Manabu× Okabe, Yoichi |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 102 | |||||
| 姓名 | 岡部, 洋一 | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | We propose a new class of SFQ logic circuits. In this new approach, an SFQ pulse represents the transition between "zero" and "one". By using these two bits of information, a one-to-one correspondence between input and output can be realized. Since the correspondence is then the same as in semiconductor circuits, this method permits logic design without clock elements. In order to carry out this logic, we propose the most fundamental element, a new DC/SFQ converter. A computer simulation and low-speed test were performed. Both results showed that this converter operates correctly with a wide margin. Moreover, this converter also pro, ides the basis for many other logic elements such as AND, OR, and XOR. | |||||
| 書誌情報 |
IEEE transactions on applied superconductivity : a publication of the IEEE Superconductivity Committee 巻 9, 号 2, p. 3729-3732, 発行日 1999-06 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 10518223 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA10791666 | |||||
| 権利 | ||||||
| 権利情報 | ©1999 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
| フォーマット | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | application/pdf | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 549.37 | |||||
| 出版者 | ||||||
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |||||
