東京大学大学院工学系研究科電気系工学専攻
Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo

Abstract

Possibility for realization of sub-0.5V extremely low power logic circuits is investigated in this thesis. Transistor variations at low power supply voltage degrade the operation of logic circuits. Thus, the effects of transistor variations are investigated at low VDD and countermeasures against them are proposed in the thesis. Reduction of power supply voltage (VDD) is an effective method for achieving ultra low power logic circuits since active power is proportional to VDD2 and leakage power is proportional to VDD. Although circuits exhibit slower speeds at low supply voltage, low voltage operation of logic circuits remains attractive for energy-constrained systems. Besides, when VDD is near/below the threshold voltage (VTH) of transistors, logic circuits operate most efficiently. In this way, lowering power supply voltage achieves low power and energy efficient operation. Transistor variations, however, inhibit lowering VDD, because the sensitivity of circuits to transistor variations drastically increases under reduced VDD. The main obstacles for low voltage operation of logic circuits are function errors and delay variations of logic circuits, because one function error at a single logic gate is considered as the function error of whole circuits and the delay variations makes the design of logic circuits more difficult at low VDD. These problems must be dealt with properly in the design of low voltage logic circuits. Thus, the purpose of the thesis is to reveal the effect of these two problems on logic circuits and propose countermeasures to achieve sub-0.5V extremely low power logic circuits. At first, function error of logic gates is discussed in 65nm CMOS. Function errors prevent lowering VDD of logic circuits. The minimum operating voltage (VDDmin) is defined as the minimum power supply voltage when the circuits operate without function errors. VDDmin increases with the number of logic gates and CMOS technology down-scaling. Thus, reducing VDDmin of logic circuits is important to achieve extremely low voltage logic circuits. The determinant factors of VDDmin in logic circuits are investigated, and the design criteria to reduce VDDmin are presented. VDDmin consists of VDDmin(SYS) and VDDmin(RAND). VDDmin(RAND) which is random component of VDDmin depends on the random variation of threshold voltage of transistors and the number of stages of logic gates, while VDDmin(SYS) which is systematic component of VDDmin is determined by the balance of nMOS and pMOS and is minimized when the logic threshold voltage is equal to half VDD. Therefore, VDDmin(RAND) is reduced by increasing width of nMOS and width of pMOS, while VDDmin(SYS) is minimized by optimizing WP/WN at a design stage. The body-biasing is effective to compensate for the increase of VDDmin(SYS) due to the die-to-die VTH variation. The optimal body-biasing minimizes VDDmin(SYS) and the forward body biasing decreases VDDmin(RAND). In the measurement, VDDmin is successfully reduced by 45mV from 193mV to 148mV by the forward body biasing. Next, the effect of delay variations on logic circuits is explored in 65nm CMOS. Delay variations of logic gates make it difficult for logic gate paths to meet timing constraints. If enough setup timing margins are considered, operation frequency decreases. By contrast, to meet hold time constraint, hold compensation buffers are inserted into logic gate paths. Therefore, the within-die delay variation dependence on VDD in several types of design under tests (DUT's) is measured with a proposed circuit. The proposed circuit emulates a real logic path because DUT's are inserted between F/F's and F/F-related delays are included in the delay measurement. The main focus of the measurement is dependence of the logic circuits on the methodology of physical layout. Although, layout of logic circuits is usually designed by automatically using place and route (P&R) tools, the effect of the auto P&R layout on delay variation is not clear at low voltage. Thus, DUT delay dependence on methodology of physical layout is investigated. The measurement result reveals that relative delay variation difference (=sigma/average) between the manual layout and the P&R layout rapidly decreases from 1.56% to 0.07% with reducing VDD from 1.2V to 0.4V, because the random delay variations due to the random transistor variations dominate total delay variations at low VDD. This result indicates that low voltage logic circuits designed by P&R tools do not raise delay variations at low VDD. Finally, in order to achieve ultra low VDD logic circuits, a post-fabrication dual VDD control (PDVC) of multiple voltage domains is proposed. Reducing VDDmin at a design phase is difficult because VDDmin is mainly determined by random variations of transistors. Furthermore, only one functional error of logic gates increases VDDmin of a whole logic circuit. Therefore, in order to reduce VDDmin, VDD must be controlled with multiple domains. In the proposed PDVC, the layout of the whole logic circuit is divided into many domains regardless of the functional blocks. The VDD of each domain is independently selected from high VDD (VDDH) and low VDD (VDDL). PDVC is applied to a DES CODEC's circuit fabricated in 65nm CMOS. The layout of DES CODEC's is generated by P&R tools and divided into 64 VDD domains. VDDH or VDDL is applied to each domain and the selection of VDD's is performed based on multiple built-in self tests. VDDH is selected in VDDmin-critical domains, while VDDL is selected in VDDmin-non-critical domains. As a result, a maximum 24% power reduction was measured with the proposed PDVC at 300kHz, VDDH =437mV, and VDDL=397mV. The results of the thesis, which includes investigation on and countermeasures against VDDmin and delay variation, is useful to realize sub-0.5V extremely low power logic circuits for future LSI applications.

発行年

2012-03-22

日本十進分類法

541

学位名

博士(工学)

学位

doctoral

学位分野

Engineering (工学)

学位授与機関

University of Tokyo (東京大学)

研究科・専攻

Department of Electrical Engineering and Information Systems, Graduate School of Engineering (工学系研究科電気系工学専攻)

学位授与年月日

2012-03-22

学位授与番号

甲第27940号

学位記番号

博工第7708号

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