{"_buckets": {"deposit": "ed7b9515-2ab2-44ba-96f4-469f6d8e5c36"}, "_deposit": {"id": "22", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "22"}, "status": "published"}, "_oai": {"id": "oai:repository.dl.itc.u-tokyo.ac.jp:00000022"}, "item_2_biblio_info_7": {"attribute_name": "\u66f8\u8a8c\u60c5\u5831", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2003-06", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "2", "bibliographicPageEnd": "546", "bibliographicPageStart": "543", "bibliographicVolumeNumber": "13", "bibliographic_titles": [{"bibliographic_title": "IEEE transactions on applied superconductivity : a publication of the IEEE Superconductivity Committee"}]}]}, "item_2_description_13": {"attribute_name": "\u30d5\u30a9\u30fc\u30de\u30c3\u30c8", "attribute_value_mlt": [{"subitem_description": "application/pdf", "subitem_description_type": "Other"}]}, "item_2_description_5": {"attribute_name": "\u6284\u9332", "attribute_value_mlt": [{"subitem_description": "Recently we have proposed Boolean single-flux-quantum (BSFQ) circuits, which like CMOS circuits directly support Boolean primitives, and do not require local synchronization for their elementary cells as well as for their combinational cells. However, only the cell-level timing description of the BSFQ circuits was considered, which did not specify their global timing strategy in a system-level design. In this paper, we present a novel global self-timing methodology, dual encoding hierarchical pipelining (DEHP), for the locally asynchronous BSFQ circuits. In circuit implementation, a nonvolatile memory cell named ND-DFF and a volatile memory cell named D-DFF have been designed.", "subitem_description_type": "Abstract"}]}, "item_2_full_name_3": {"attribute_name": "\u8457\u8005\u5225\u540d", "attribute_value_mlt": [{"nameIdentifiers": [{"nameIdentifier": "94", "nameIdentifierScheme": "WEKO"}], "names": [{"name": "\u5ca1\u90e8, \u6d0b\u4e00"}]}]}, "item_2_publisher_20": {"attribute_name": "\u51fa\u7248\u8005", "attribute_value_mlt": [{"subitem_publisher": "IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC"}]}, "item_2_rights_12": {"attribute_name": "\u6a29\u5229", "attribute_value_mlt": [{"subitem_rights": "\u00a92003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE."}]}, "item_2_source_id_10": {"attribute_name": "\u66f8\u8a8c\u30ec\u30b3\u30fc\u30c9ID", "attribute_value_mlt": [{"subitem_source_identifier": "AA10791666", "subitem_source_identifier_type": "NCID"}]}, "item_2_source_id_8": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "10518223", "subitem_source_identifier_type": "ISSN"}]}, "item_2_subject_15": {"attribute_name": "\u65e5\u672c\u5341\u9032\u5206\u985e\u6cd5", "attribute_value_mlt": [{"subitem_subject": "549.3", "subitem_subject_scheme": "NDC"}]}, "item_2_text_34": {"attribute_name": "\u8cc7\u6e90\u30bf\u30a4\u30d7", "attribute_value_mlt": [{"subitem_text_value": "Journal Article"}]}, "item_creator": {"attribute_name": "\u8457\u8005", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Teh, CK"}], "nameIdentifiers": [{"nameIdentifier": "92", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Okabe, Yoichi"}], "nameIdentifiers": [{"nameIdentifier": "93", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "\u30d5\u30a1\u30a4\u30eb\u60c5\u5831", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-05-30"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "IEEE_A_S_2003_13_2.pdf", "filesize": [{"value": "505.2 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 505200.0, "url": {"label": "IEEE_A_S_2003_13_2.pdf", "url": "https://repository.dl.itc.u-tokyo.ac.jp/record/22/files/IEEE_A_S_2003_13_2.pdf"}, "version_id": "58948b8c-1658-4a18-994c-d7b307848577"}]}, "item_keyword": {"attribute_name": "\u30ad\u30fc\u30ef\u30fc\u30c9", "attribute_value_mlt": [{"subitem_subject": "asynchronous design", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Boolean primitive", "subitem_subject_scheme": "Other"}, {"subitem_subject": "BSFQ", "subitem_subject_scheme": "Other"}, {"subitem_subject": "pipelining", "subitem_subject_scheme": "Other"}, {"subitem_subject": "self-timing", "subitem_subject_scheme": "Other"}, {"subitem_subject": "SFQ circuits", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "\u8a00\u8a9e", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "\u8cc7\u6e90\u30bf\u30a4\u30d7", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "A novel global self-timing methodology for BSFQ circuits", "item_titles": {"attribute_name": "\u30bf\u30a4\u30c8\u30eb", "attribute_value_mlt": [{"subitem_title": "A novel global self-timing methodology for BSFQ circuits"}]}, "item_type_id": "2", "owner": "1", "path": ["12/13", "9/10/14"], "permalink_uri": "http://hdl.handle.net/2261/34", "pubdate": {"attribute_name": "\u516c\u958b\u65e5", "attribute_value": "2006-02-13"}, "publish_date": "2006-02-13", "publish_status": "0", "recid": "22", "relation": {}, "relation_version_is_last": true, "title": ["A novel global self-timing methodology for BSFQ circuits"], "weko_shared_id": null}