WEKO3
アイテム
A novel global self-timing methodology for BSFQ circuits
http://hdl.handle.net/2261/34
http://hdl.handle.net/2261/34856871b1-f423-4dab-91bd-1844142edc63
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
IEEE_A_S_2003_13_2.pdf (505.2 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2006-02-13 | |||||
| タイトル | ||||||
| タイトル | A novel global self-timing methodology for BSFQ circuits | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | asynchronous design | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Boolean primitive | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | BSFQ | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | pipelining | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | self-timing | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | SFQ circuits | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 著者 |
Teh, CK
× Teh, CK× Okabe, Yoichi |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 94 | |||||
| 姓名 | 岡部, 洋一 | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Recently we have proposed Boolean single-flux-quantum (BSFQ) circuits, which like CMOS circuits directly support Boolean primitives, and do not require local synchronization for their elementary cells as well as for their combinational cells. However, only the cell-level timing description of the BSFQ circuits was considered, which did not specify their global timing strategy in a system-level design. In this paper, we present a novel global self-timing methodology, dual encoding hierarchical pipelining (DEHP), for the locally asynchronous BSFQ circuits. In circuit implementation, a nonvolatile memory cell named ND-DFF and a volatile memory cell named D-DFF have been designed. | |||||
| 書誌情報 |
IEEE transactions on applied superconductivity : a publication of the IEEE Superconductivity Committee 巻 13, 号 2, p. 543-546, 発行日 2003-06 |
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| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 10518223 | |||||
| 書誌レコードID | ||||||
| 収録物識別子タイプ | NCID | |||||
| 収録物識別子 | AA10791666 | |||||
| 権利 | ||||||
| 権利情報 | ©2003 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
| フォーマット | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | application/pdf | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 549.3 | |||||
| 出版者 | ||||||
| 出版者 | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | |||||
