WEKO3
アイテム
{"_buckets": {"deposit": "541ab971-a8d8-4e86-9281-f4252a65d402"}, "_deposit": {"id": "2805", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "2805"}, "status": "published"}, "_oai": {"id": "oai:repository.dl.itc.u-tokyo.ac.jp:00002805", "sets": ["280", "318"]}, "item_7_alternative_title_1": {"attribute_name": "その他のタイトル", "attribute_value_mlt": [{"subitem_alternative_title": "大規模集積回路におけるスタンダードセルレイアウトの最適自動合成手法"}]}, "item_7_biblio_info_7": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2007-03-22", "bibliographicIssueDateType": "Issued"}, "bibliographic_titles": [{}]}]}, "item_7_date_granted_25": {"attribute_name": "学位授与年月日", "attribute_value_mlt": [{"subitem_dategranted": "2007-03-22"}]}, "item_7_degree_grantor_23": {"attribute_name": "学位授与機関", "attribute_value_mlt": [{"subitem_degreegrantor": [{"subitem_degreegrantor_name": "University of Tokyo (東京大学)"}]}]}, "item_7_degree_name_20": {"attribute_name": "学位名", "attribute_value_mlt": [{"subitem_degreename": "博士(工学)"}]}, "item_7_description_5": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "The recent progress in VLSI process technologies enables us to integrate a large number of transistors on one chip, and significantly improves the circuit performance. On the other hand, due to the ever-increasing design complexity of the VLSI, we could never design any competitive SoCs within practical time-to-market without automated design techniques. One of the major automated design methodologies for designing VLSIs is the cell-based design. In this design flow, we use a standard-cell library. The characteristics of cells including cell delay, area, and power as well as yield are used in the logic synthesis stage, and the physical layout of each cell is used in the place \u0026 route stage. As is clear from this design flow, standard cells are the most fundamental components of VLSI, and provide the building blocks for creating large complex functions in both application-specific and semi-custom domains. Therefore, their performance has significant effects on the final performance of the synthesized VLSI. This thesis focuses on the optimization methods for standard-cell layouts. We propose minimum-width transistor placement and intra-cell routing via Boolean satisfiability to optimize the area of the cell layouts. We also propose a comprehensive cell layout synthesis method and a cell layout de-compaction method for yield optimization.//Chapter 2 proposes a minimum-width layout synthesis method for dual CMOS cells via Boolean Satisfiability (SAT). Cell layout synthesis problems, i.e., the transistor placement and the intra-cell routing problems are first transformed into SAT problems by this formulation. The proposed method guarantees to generate the minimum-width cells with routability under our layout styles. This method places complementary P and N type transistors individually during transistor placement, and can generate smaller width layout compared with the case of pairing the complementary P and N type transistors. Our method generates the cell layouts of 30 static dual CMOS logic circuits in 58% runtime with only 5% area increase compared with the commercial cell generation tool with cell layout compaction. This result shows that our cell layout styles defined for the SAT formulation is practical enough to generate the layout quickly with a little area overhead. Since this method still has a restriction in gate connection style between P and N type transistors, it is applicable only to dual CMOS cells. The extension of the transistor placement method to non-dual cells is explained in Chapter 4.//Chapter 3 describes a hierarchical extension of the cell layout synthesis method proposed in Chapter 2 for the cell layout synthesis of large dual CMOS cells. This method partitions a given transistor-level netlist into blocks considering the transistor connections by diffusions. Intra-block placement uses an exact transistor placement method proposed in Chapter 2, and hierarchically generates the transistor placement with routability. The comparison results with the flat cell layout synthesis method for 30 benchmark circuits show that the proposed method generates the same width layout as the flat method except one circuit and drastically reduces the runtime for cell layout synthesis. The comparison results with the commercial cell generation tool without cell layout compaction show that the total cell width of the proposed method is increased about 4% due to the layout style restriction, whereas the runtime is only about 3% of that of the commercial tool. From these results, we can conclude that the proposed method can be used as a quick layout generator in the area of transistor-level circuit optimization such as on-demand cell layout synthesis.//Chapter 4 shows flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors, whereas the cell layout synthesis methods proposed in the previous chapters are only for dual cells. This chapter targets the minimum-width transistor placement, and does not take the intra-cell routings into consideration. Our approaches are the first exact transistor placement method which can be applied to CMOS cells with any types of structure, whereas almost all of the conventional exact transistor placement method is applicable only to dual CMOS cells. Since non-dual CMOS cells occupy a major part of an industrial standard-cell library, the exact minimum-width transistor placement should be applied even to non-dual CMOS cells. The flat single-row approach generates smaller width placement for 29 out of 103 dual cells than the transistor placement method for dual cells explained in Chapter 2 which theoretically generates the smallest width placement among the existing exact methods. The experimental results show that it is not only applicable to CMOS cells with any types of structure, but also more effective even for dual CMOS cells compared with the transistor placement method only for dual cells. The hierarchical single-row approach which is based on circuit partitioning reduces the runtime drastically and generates 81% of 340 cells in an industrial standard-cell library of a 90nm technology within one hour for each cell, whereas the flat approach and the exact method for dual cells generates 43% and 32%, respectively. This chapter also shows the generalization results of the single-row transistor placement method into the multi-row placement and proposes an exact minimum-width multi-row transistor placement method for general CMOS cells. The experimental results of the multi-row placement method show that the proposed method generates more area-efficient placement than the conventional method only for dual cells by using the gate connection style which is more suitable for multi-row transistor placement than the conventional style, and can solve the cells with up to 26 transistors in reasonable runtime.//Chapter 5 introduces a cell layout synthesis technique to optimize the yield. The yield cost metric used in the proposed method is the sensitivity to wiring faults due to spot defects. The sensitivity to faults on intra-cell routings is modeled with consideration to the spot defects size distribution and the end effect of critical areas. The effect of the sensitivity reduction on the yield is also discussed in this chapter. The minimum-width cell layout of CMOS logic cells are comprehensively generated using the transistor placement method proposed in Chapter 2 and the comprehensive intra-cell routing method proposed in this chapter. The yield optimal layouts are selected from the exhaustively-generated layouts by using the proposed sensitivity to wiring faults as a cost function. Our cell layout synthesis technique generates the minimum width layouts of CMOS logic cells comprehensively, and selects the optimal layouts based on the cost functions. The experimental results on our comprehensive layout synthesis method to 8 CMOS logic circuits which have up to 14 transistors show that the fault sensitivities are reduced about 15% on an average by selecting the minimum-sensitivity layouts rather than selecting the minimum-wire-length layouts. Our layout synthesis method is applicable for deriving the optimal cell layouts by some other cost metrics, such as power, delay, and signal integrity, if reasonable cost functions are given.//Chapter 6 proposes a timing-aware cell layout de-compaction method for yield optimization using Linear Programming (LP). The proposed method performs a de-compaction of the original layout in order to improve the yield by minimizing the Critical Area (CA) inside the cell. This yield improvement procedure is executed under given timing constraints. To formulate the timing constraints as LP, a new accurate linear delay model which approximates the difference from the original delay is also proposed. The effectiveness of the proposed method for OPC mask data volume reduction is also shown in this chapter. This timing-aware de-compaction framework is extended to the redundant contact insertion adjacent to the original single contacts to minimize the yield loss due to contact failure. To take the parametric yield into account, the proposed method is also extended to the gate layout pattern regularity enhancement to reduce the systematic variation of the gate critical dimensions (CD). Experimental results show that the developed delay model is accurate enough to constrain the delay during de-compaction. The CA is correctly minimized under given timing constraint, and the maximum CA reduction is about 25% on an average of 8 cells. Experimental results on a 90nm cell layouts show that the proposed method is also effective for OPC mask data volume reduction and reduces the fractured mask data size 4.28% on an average in the case that 10% delay increase is allowed. The proposed redundant contact insertion method under the timing-aware de-compaction framework inserts the redundant contacts as many as possible under given timing and area constraints using LP. The extension of the de-compaction method to a gate layout pattern regularity enhancement is also shown to be effective to reduce the systematic variation of the gate CD. With 10% allowable delay increase, 73.7% gates of 25 cells in a 90nm technology are placed perfectly on-pitch by the proposed method. Experiment on the edge placement error (EPE) estimation shows that the standard deviation of the gate CD EPE distribution is reduced by about 28% compared with that of the original layouts. The proposed timing-aware yield enhancement method enables us to explore the trade-off between performance and yield. We can pick up the yield/performance variants from the trade-off curve and provide a yield-enhanced library. The proposed method is the essential technique to realize the yield-aware VLSI design methodologies.//We are sure that these results in this thesis such as the exact minimum-width cell layout synthesis techniques, the comprehensive cell layout synthesis method, and the cell layout de-compaction method for yield optimization will be used for standard-cell layout optimization in terms of area, delay, and yield, and contribute to the VLSI performance and reliability improvements.", "subitem_description_type": "Abstract"}]}, "item_7_dissertation_number_26": {"attribute_name": "学位授与番号", "attribute_value_mlt": [{"subitem_dissertationnumber": "甲第22286号"}]}, "item_7_full_name_3": {"attribute_name": "著者別名", "attribute_value_mlt": [{"nameIdentifiers": [{"nameIdentifier": "7382", "nameIdentifierScheme": "WEKO"}], "names": [{"name": "飯塚, 哲也"}]}]}, "item_7_identifier_registration": {"attribute_name": "ID登録", "attribute_value_mlt": [{"subitem_identifier_reg_text": "10.15083/00002799", "subitem_identifier_reg_type": "JaLC"}]}, "item_7_select_21": {"attribute_name": "学位", "attribute_value_mlt": [{"subitem_select_item": "doctoral"}]}, "item_7_subject_13": {"attribute_name": "日本十進分類法", "attribute_value_mlt": [{"subitem_subject": "549", "subitem_subject_scheme": "NDC"}]}, "item_7_text_22": {"attribute_name": "学位分野", "attribute_value_mlt": [{"subitem_text_value": "Engineering (工学)"}]}, "item_7_text_24": {"attribute_name": "研究科・専攻", "attribute_value_mlt": [{"subitem_text_value": "Department of Electronic Engineering, Graduate School of Engineering (工学系研究科電子工学専攻)"}]}, "item_7_text_27": {"attribute_name": "学位記番号", "attribute_value_mlt": [{"subitem_text_value": "博工第6491号"}]}, "item_7_text_36": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"subitem_text_value": "Thesis"}]}, "item_7_text_4": {"attribute_name": "著者所属", "attribute_value_mlt": [{"subitem_text_value": "東京大学大学院工学系研究科電子工学専攻"}, {"subitem_text_value": "Department of Electronic Engineering, Graduate School of Engineering, The University of Tokyo"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Iizuka, Tetsuya"}], "nameIdentifiers": [{"nameIdentifier": "7381", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-05-31"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "K-122286-1.pdf", "filesize": [{"value": "5.1 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 5100000.0, "url": {"label": "K-122286-1.pdf", "url": "https://repository.dl.itc.u-tokyo.ac.jp/record/2805/files/K-122286-1.pdf"}, "version_id": "8d45acb7-90f1-4039-81f0-6d4f9e9aba05"}, {"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-05-31"}], "displaytype": "detail", "download_preview_message": "", "file_order": 1, "filename": "K-122286-2.pdf", "filesize": [{"value": "4.9 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 4900000.0, "url": {"label": "K-122286-2.pdf", "url": "https://repository.dl.itc.u-tokyo.ac.jp/record/2805/files/K-122286-2.pdf"}, "version_id": "fb16fd16-1795-4ebe-a225-f3b89719c6f4"}, {"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-05-31"}], "displaytype": "detail", "download_preview_message": "", "file_order": 2, "filename": "K-122286-3.pdf", "filesize": [{"value": "6.1 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 6100000.0, "url": {"label": "K-122286-3.pdf", "url": "https://repository.dl.itc.u-tokyo.ac.jp/record/2805/files/K-122286-3.pdf"}, "version_id": "706c3412-4d81-4c30-891c-d98158d63eb6"}, {"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-05-31"}], "displaytype": "detail", "download_preview_message": "", "file_order": 3, "filename": "K-122286-4.pdf", "filesize": [{"value": "5.9 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 5900000.0, "url": {"label": "K-122286-4.pdf", "url": "https://repository.dl.itc.u-tokyo.ac.jp/record/2805/files/K-122286-4.pdf"}, "version_id": "2df22286-afb4-4a4f-8405-0016c0d1de16"}, {"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-05-31"}], "displaytype": "detail", "download_preview_message": "", "file_order": 4, "filename": "K-122286-5.pdf", "filesize": [{"value": "5.2 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 5200000.0, "url": {"label": "K-122286-5.pdf", "url": "https://repository.dl.itc.u-tokyo.ac.jp/record/2805/files/K-122286-5.pdf"}, "version_id": "8c414e5f-0b89-46ab-b910-ba6a58635849"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "thesis", "resourceuri": "http://purl.org/coar/resource_type/c_46ec"}]}, "item_title": "Optimal Layout Synthesis of Standard Cells in Large Scale Integration", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Optimal Layout Synthesis of Standard Cells in Large Scale Integration"}]}, "item_type_id": "7", "owner": "1", "path": ["280", "318"], "permalink_uri": "https://doi.org/10.15083/00002799", "pubdate": {"attribute_name": "公開日", "attribute_value": "2012-03-01"}, "publish_date": "2012-03-01", "publish_status": "0", "recid": "2805", "relation": {}, "relation_version_is_last": true, "title": ["Optimal Layout Synthesis of Standard Cells in Large Scale Integration"], "weko_shared_id": null}
Optimal Layout Synthesis of Standard Cells in Large Scale Integration
https://doi.org/10.15083/00002799
https://doi.org/10.15083/000027995c183d34-458c-4adf-8ad8-08da35f0407d
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Item type | 学位論文 / Thesis or Dissertation(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2012-03-01 | |||||
タイトル | ||||||
タイトル | Optimal Layout Synthesis of Standard Cells in Large Scale Integration | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源 | http://purl.org/coar/resource_type/c_46ec | |||||
タイプ | thesis | |||||
ID登録 | ||||||
ID登録 | 10.15083/00002799 | |||||
ID登録タイプ | JaLC | |||||
その他のタイトル | ||||||
その他のタイトル | 大規模集積回路におけるスタンダードセルレイアウトの最適自動合成手法 | |||||
著者 |
Iizuka, Tetsuya
× Iizuka, Tetsuya |
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著者別名 | ||||||
識別子 | 7382 | |||||
識別子Scheme | WEKO | |||||
姓名 | 飯塚, 哲也 | |||||
著者所属 | ||||||
著者所属 | 東京大学大学院工学系研究科電子工学専攻 | |||||
著者所属 | ||||||
著者所属 | Department of Electronic Engineering, Graduate School of Engineering, The University of Tokyo | |||||
Abstract | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | The recent progress in VLSI process technologies enables us to integrate a large number of transistors on one chip, and significantly improves the circuit performance. On the other hand, due to the ever-increasing design complexity of the VLSI, we could never design any competitive SoCs within practical time-to-market without automated design techniques. One of the major automated design methodologies for designing VLSIs is the cell-based design. In this design flow, we use a standard-cell library. The characteristics of cells including cell delay, area, and power as well as yield are used in the logic synthesis stage, and the physical layout of each cell is used in the place & route stage. As is clear from this design flow, standard cells are the most fundamental components of VLSI, and provide the building blocks for creating large complex functions in both application-specific and semi-custom domains. Therefore, their performance has significant effects on the final performance of the synthesized VLSI. This thesis focuses on the optimization methods for standard-cell layouts. We propose minimum-width transistor placement and intra-cell routing via Boolean satisfiability to optimize the area of the cell layouts. We also propose a comprehensive cell layout synthesis method and a cell layout de-compaction method for yield optimization.//Chapter 2 proposes a minimum-width layout synthesis method for dual CMOS cells via Boolean Satisfiability (SAT). Cell layout synthesis problems, i.e., the transistor placement and the intra-cell routing problems are first transformed into SAT problems by this formulation. The proposed method guarantees to generate the minimum-width cells with routability under our layout styles. This method places complementary P and N type transistors individually during transistor placement, and can generate smaller width layout compared with the case of pairing the complementary P and N type transistors. Our method generates the cell layouts of 30 static dual CMOS logic circuits in 58% runtime with only 5% area increase compared with the commercial cell generation tool with cell layout compaction. This result shows that our cell layout styles defined for the SAT formulation is practical enough to generate the layout quickly with a little area overhead. Since this method still has a restriction in gate connection style between P and N type transistors, it is applicable only to dual CMOS cells. The extension of the transistor placement method to non-dual cells is explained in Chapter 4.//Chapter 3 describes a hierarchical extension of the cell layout synthesis method proposed in Chapter 2 for the cell layout synthesis of large dual CMOS cells. This method partitions a given transistor-level netlist into blocks considering the transistor connections by diffusions. Intra-block placement uses an exact transistor placement method proposed in Chapter 2, and hierarchically generates the transistor placement with routability. The comparison results with the flat cell layout synthesis method for 30 benchmark circuits show that the proposed method generates the same width layout as the flat method except one circuit and drastically reduces the runtime for cell layout synthesis. The comparison results with the commercial cell generation tool without cell layout compaction show that the total cell width of the proposed method is increased about 4% due to the layout style restriction, whereas the runtime is only about 3% of that of the commercial tool. From these results, we can conclude that the proposed method can be used as a quick layout generator in the area of transistor-level circuit optimization such as on-demand cell layout synthesis.//Chapter 4 shows flat and hierarchical approaches for generating a minimum-width transistor placement of CMOS cells in presence of non-dual P and N type transistors, whereas the cell layout synthesis methods proposed in the previous chapters are only for dual cells. This chapter targets the minimum-width transistor placement, and does not take the intra-cell routings into consideration. Our approaches are the first exact transistor placement method which can be applied to CMOS cells with any types of structure, whereas almost all of the conventional exact transistor placement method is applicable only to dual CMOS cells. Since non-dual CMOS cells occupy a major part of an industrial standard-cell library, the exact minimum-width transistor placement should be applied even to non-dual CMOS cells. The flat single-row approach generates smaller width placement for 29 out of 103 dual cells than the transistor placement method for dual cells explained in Chapter 2 which theoretically generates the smallest width placement among the existing exact methods. The experimental results show that it is not only applicable to CMOS cells with any types of structure, but also more effective even for dual CMOS cells compared with the transistor placement method only for dual cells. The hierarchical single-row approach which is based on circuit partitioning reduces the runtime drastically and generates 81% of 340 cells in an industrial standard-cell library of a 90nm technology within one hour for each cell, whereas the flat approach and the exact method for dual cells generates 43% and 32%, respectively. This chapter also shows the generalization results of the single-row transistor placement method into the multi-row placement and proposes an exact minimum-width multi-row transistor placement method for general CMOS cells. The experimental results of the multi-row placement method show that the proposed method generates more area-efficient placement than the conventional method only for dual cells by using the gate connection style which is more suitable for multi-row transistor placement than the conventional style, and can solve the cells with up to 26 transistors in reasonable runtime.//Chapter 5 introduces a cell layout synthesis technique to optimize the yield. The yield cost metric used in the proposed method is the sensitivity to wiring faults due to spot defects. The sensitivity to faults on intra-cell routings is modeled with consideration to the spot defects size distribution and the end effect of critical areas. The effect of the sensitivity reduction on the yield is also discussed in this chapter. The minimum-width cell layout of CMOS logic cells are comprehensively generated using the transistor placement method proposed in Chapter 2 and the comprehensive intra-cell routing method proposed in this chapter. The yield optimal layouts are selected from the exhaustively-generated layouts by using the proposed sensitivity to wiring faults as a cost function. Our cell layout synthesis technique generates the minimum width layouts of CMOS logic cells comprehensively, and selects the optimal layouts based on the cost functions. The experimental results on our comprehensive layout synthesis method to 8 CMOS logic circuits which have up to 14 transistors show that the fault sensitivities are reduced about 15% on an average by selecting the minimum-sensitivity layouts rather than selecting the minimum-wire-length layouts. Our layout synthesis method is applicable for deriving the optimal cell layouts by some other cost metrics, such as power, delay, and signal integrity, if reasonable cost functions are given.//Chapter 6 proposes a timing-aware cell layout de-compaction method for yield optimization using Linear Programming (LP). The proposed method performs a de-compaction of the original layout in order to improve the yield by minimizing the Critical Area (CA) inside the cell. This yield improvement procedure is executed under given timing constraints. To formulate the timing constraints as LP, a new accurate linear delay model which approximates the difference from the original delay is also proposed. The effectiveness of the proposed method for OPC mask data volume reduction is also shown in this chapter. This timing-aware de-compaction framework is extended to the redundant contact insertion adjacent to the original single contacts to minimize the yield loss due to contact failure. To take the parametric yield into account, the proposed method is also extended to the gate layout pattern regularity enhancement to reduce the systematic variation of the gate critical dimensions (CD). Experimental results show that the developed delay model is accurate enough to constrain the delay during de-compaction. The CA is correctly minimized under given timing constraint, and the maximum CA reduction is about 25% on an average of 8 cells. Experimental results on a 90nm cell layouts show that the proposed method is also effective for OPC mask data volume reduction and reduces the fractured mask data size 4.28% on an average in the case that 10% delay increase is allowed. The proposed redundant contact insertion method under the timing-aware de-compaction framework inserts the redundant contacts as many as possible under given timing and area constraints using LP. The extension of the de-compaction method to a gate layout pattern regularity enhancement is also shown to be effective to reduce the systematic variation of the gate CD. With 10% allowable delay increase, 73.7% gates of 25 cells in a 90nm technology are placed perfectly on-pitch by the proposed method. Experiment on the edge placement error (EPE) estimation shows that the standard deviation of the gate CD EPE distribution is reduced by about 28% compared with that of the original layouts. The proposed timing-aware yield enhancement method enables us to explore the trade-off between performance and yield. We can pick up the yield/performance variants from the trade-off curve and provide a yield-enhanced library. The proposed method is the essential technique to realize the yield-aware VLSI design methodologies.//We are sure that these results in this thesis such as the exact minimum-width cell layout synthesis techniques, the comprehensive cell layout synthesis method, and the cell layout de-compaction method for yield optimization will be used for standard-cell layout optimization in terms of area, delay, and yield, and contribute to the VLSI performance and reliability improvements. | |||||
書誌情報 | 発行日 2007-03-22 | |||||
日本十進分類法 | ||||||
主題 | 549 | |||||
主題Scheme | NDC | |||||
学位名 | ||||||
学位名 | 博士(工学) | |||||
学位 | ||||||
値 | doctoral | |||||
学位分野 | ||||||
Engineering (工学) | ||||||
学位授与機関 | ||||||
学位授与機関名 | University of Tokyo (東京大学) | |||||
研究科・専攻 | ||||||
Department of Electronic Engineering, Graduate School of Engineering (工学系研究科電子工学専攻) | ||||||
学位授与年月日 | ||||||
学位授与年月日 | 2007-03-22 | |||||
学位授与番号 | ||||||
学位授与番号 | 甲第22286号 | |||||
学位記番号 | ||||||
博工第6491号 |