{"_buckets": {"deposit": "9e5dd37f-5f46-4420-b559-f407029d00cd"}, "_deposit": {"id": "5424", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "5424"}, "status": "published"}, "_oai": {"id": "oai:repository.dl.itc.u-tokyo.ac.jp:00005424"}, "item_7_alternative_title_1": {"attribute_name": "\u305d\u306e\u4ed6\u306e\u30bf\u30a4\u30c8\u30eb", "attribute_value_mlt": [{"subitem_alternative_title": "\u30b7\u30ea\u30b3\u30f3\u30ca\u30ce\u30ef\u30a4\u30e4MOSFET\u306b\u304a\u3051\u308b\u30ad\u30e3\u30ea\u30a2\u79fb\u52d5\u5ea6\u3068\u7279\u6027\u3070\u3089\u3064\u304d\u306b\u95a2\u3059\u308b\u7814\u7a76"}]}, "item_7_biblio_info_7": {"attribute_name": "\u66f8\u8a8c\u60c5\u5831", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2012-09-27", "bibliographicIssueDateType": "Issued"}, "bibliographic_titles": [{}]}]}, "item_7_date_granted_25": {"attribute_name": "\u5b66\u4f4d\u6388\u4e0e\u5e74\u6708\u65e5", "attribute_value_mlt": [{"subitem_dategranted": "2012-09-27"}]}, "item_7_degree_grantor_23": {"attribute_name": "\u5b66\u4f4d\u6388\u4e0e\u6a5f\u95a2", "attribute_value_mlt": [{"subitem_degreegrantor": [{"subitem_degreegrantor_name": "University of Tokyo (\u6771\u4eac\u5927\u5b66)"}]}]}, "item_7_degree_name_20": {"attribute_name": "\u5b66\u4f4d\u540d", "attribute_value_mlt": [{"subitem_degreename": "\u535a\u58eb(\u5de5\u5b66)"}]}, "item_7_description_5": {"attribute_name": "\u6284\u9332", "attribute_value_mlt": [{"subitem_description": "In the past several decades, the size of a metal-oxide-semiconductor field-effect-transistor (MOSFET), the basic element in very-large-scale integrated circuits (VLSI), has been scaled down for higher integration and higher performance. As of 2012, the gate length of MOSFETs has reached a sub-30 nm regime. However, as the scaling proceeds, several problems stand out and prevent more miniaturization of MOSFETs. Among all the issues which arise to handicap the continuous device scaling, two issues are with great importance, one is the short channel effect (SCE), and the other is the variability. Among all the promising post-planar structures proposed for solving the scaling issues, the silicon nanowire MOSFETs, have attracted much attention in recent year, for their high immunity to short-channel effect. The purpose of this work is to evaluate the potential of silicon nanowire MOSFETs for promising \u201cMore Moore\u201d device in terms of both device performance enhancement and stability improvement. In this work, silicon nanowire FETs with tri-gate structure is extensively studied for carrier mobility and variability. This work is based mainly on the experiments including device design, sample fabrication and characteristic measurement. In this paper, on the base of split C-V method, experimental and theoretical investigations of carrier mobility characteristics in single silicon nanowires are described systematically for the first time. The hole mobility in [110]-direction silicon nanowires is higher than (100) universal curve even in a single nanowire FET, which originates from the effect of (110) side surface with high hole mobility. Low temperature measurements were performed with [110]- direction NWs on (100) SOI to investigate the scattering mechanisms in tri-gate silicon nanowire. Surface roughness limited mobility and phonon limited mobility are extracted and analyzed. It is found that the orientation and roughness quality of nanowire surface plays the key role that determinates the mobility modulation in nanowires. And, it is experimentally found that within-device variability of not only VTH but also those of DIBL and COV are suppressed in intrinsic channel nanowire FETs owing to the non intentionally doped channel and the absence of gate work-function variability. The intrinsic channel silicon nanowire MOSFET is promising for a future scaled device structure in terms of not only the short channel effect suppression but also the variability suppression. In conclusion, the results obtained in this thesis show important information on the carrier mobility and variability characteristics in silicon nanowire MOSFETs, which are promising for a future scaled device structure in terms of not only the short channel effect suppression but also the performance enhancement and variability suppression.", "subitem_description_type": "Abstract"}]}, "item_7_full_name_3": {"attribute_name": "\u8457\u8005\u5225\u540d", "attribute_value_mlt": [{"nameIdentifiers": [{"nameIdentifier": "11327", "nameIdentifierScheme": "WEKO"}], "names": [{"name": "\u6bdb, \u73c2"}]}]}, "item_7_identifier_registration": {"attribute_name": "ID\u767b\u9332", "attribute_value_mlt": [{"subitem_identifier_reg_text": "10.15083/00005415", "subitem_identifier_reg_type": "JaLC"}]}, "item_7_select_21": {"attribute_name": "\u5b66\u4f4d", "attribute_value_mlt": [{"subitem_select_item": "doctoral"}]}, "item_7_subject_13": {"attribute_name": "\u65e5\u672c\u5341\u9032\u5206\u985e\u6cd5", "attribute_value_mlt": [{"subitem_subject": "549", "subitem_subject_scheme": "NDC"}]}, "item_7_text_22": {"attribute_name": "\u5b66\u4f4d\u5206\u91ce", "attribute_value_mlt": [{"subitem_text_value": "Engineering (\u5de5\u5b66)"}]}, "item_7_text_24": {"attribute_name": "\u7814\u7a76\u79d1\u30fb\u5c02\u653b", "attribute_value_mlt": [{"subitem_text_value": "Department of Electrical Engineering and Information Systems, Graduate School of Engineering (\u5de5\u5b66\u7cfb\u7814\u7a76\u79d1\u96fb\u6c17\u7cfb\u5de5\u5b66\u5c02\u653b)"}]}, "item_7_text_36": {"attribute_name": "\u8cc7\u6e90\u30bf\u30a4\u30d7", "attribute_value_mlt": [{"subitem_text_value": "Thesis"}]}, "item_7_text_4": {"attribute_name": "\u8457\u8005\u6240\u5c5e", "attribute_value_mlt": [{"subitem_text_value": "\u6771\u4eac\u5927\u5b66\u5927\u5b66\u9662\u5de5\u5b66\u7cfb\u7814\u7a76\u79d1\u96fb\u6c17\u7cfb\u5de5\u5b66\u5c02\u653b"}, {"subitem_text_value": "Department of Electrical Engineering and Information Systems, Graduate School of Engineering, The University of Tokyo"}]}, "item_creator": {"attribute_name": "\u8457\u8005", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Mao, Ke"}], "nameIdentifiers": [{"nameIdentifier": "11326", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "\u30d5\u30a1\u30a4\u30eb\u60c5\u5831", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2017-06-01"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "37087291.pdf", "filesize": [{"value": "1.6 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 1600000.0, "url": {"label": "37087291.pdf", "url": "https://repository.dl.itc.u-tokyo.ac.jp/record/5424/files/37087291.pdf"}, "version_id": "d03f6db7-fe87-4dcf-86b9-a32718ed4d18"}]}, "item_language": {"attribute_name": "\u8a00\u8a9e", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "\u8cc7\u6e90\u30bf\u30a4\u30d7", "attribute_value_mlt": [{"resourcetype": "thesis", "resourceuri": "http://purl.org/coar/resource_type/c_46ec"}]}, "item_title": "A Study of Carrier Mobility and Variability in Silicon Nanowire MOSFETs", "item_titles": {"attribute_name": "\u30bf\u30a4\u30c8\u30eb", "attribute_value_mlt": [{"subitem_title": "A Study of Carrier Mobility and Variability in Silicon Nanowire MOSFETs"}]}, "item_type_id": "7", "owner": "1", "path": ["9/233/280", "6/209/392"], "permalink_uri": "https://doi.org/10.15083/00005415", "pubdate": {"attribute_name": "\u516c\u958b\u65e5", "attribute_name_i18n": "\u516c\u958b\u65e5", "attribute_value": "2013-10-02"}, "publish_date": "2013-10-02", "publish_status": "0", "recid": "5424", "relation": {}, "relation_version_is_last": true, "title": ["A Study of Carrier Mobility and Variability in Silicon Nanowire MOSFETs"], "weko_shared_id": null}