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  1. 113 工学系研究科・工学部
  2. 21 電子工学専攻
  3. 1132220 博士論文(電子工学専攻)
  1. 0 資料タイプ別
  2. 20 学位論文
  3. 021 博士論文

CMOS Array Logic Architectures Using Dual-Rail Threshold Logic Circuits

https://doi.org/10.15083/00008827
9bbd94ad-bfec-48b2-9e61-79ebd11f48f4
名前 / ファイル ライセンス アクション
119025.pdf 119025.pdf (12.4 MB)
Item type 学位論文 / Thesis or Dissertation(1)
公開日 2017-01-13
タイトル
タイトル CMOS Array Logic Architectures Using Dual-Rail Threshold Logic Circuits
言語
言語 eng
キーワード
主題 集積回路
主題Scheme Other
資源タイプ
資源 http://purl.org/coar/resource_type/c_46ec
タイプ thesis
ID登録
ID登録 10.15083/00008827
ID登録タイプ JaLC
その他のタイトル
その他のタイトル 2線式しきい値論理回路を用いた配列型CMOS論理アーキテクチャに関する研究
著者 Yamaoka, Akihiro

× Yamaoka, Akihiro

WEKO 17836

Yamaoka, Akihiro

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著者別名
識別子
識別子 17837
識別子Scheme WEKO
姓名
姓名 山岡, 寛明
著者所属
著者所属 東京大学大学院工学系研究科 電子工学専攻
書誌情報 発行日 2004-03-25
日本十進分類法
主題 549.7
主題Scheme NDC
学位名
学位名 博士(工学)
学位
値 doctoral
学位分野
Engineering (工学)
学位授与機関
学位授与機関名
学位授与機関名 University of Tokyo (東京大学)
研究科・専攻
Department of Electronic Engineering, Graduate School of Engineering (工学系研究科電子工学専攻)
学位授与年月日
学位授与年月日 2004-03-25
学位授与番号
学位授与番号 甲第19025号
学位記番号
博工第5757号
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