WEKO3
アイテム
Design of Microcontroller with Completion Detection Capability by using Dual-Rail Domino Circuit
http://hdl.handle.net/2261/50151
http://hdl.handle.net/2261/501511ebbdaa5-9659-438a-9d01-89678ae9ef19
| 名前 / ファイル | ライセンス | アクション |
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K-M1243-1.pdf (6.3 MB)
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K-M1243-2.pdf (5.4 MB)
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K-M1243-3.pdf (5.4 MB)
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| Item type | 学位論文 / Thesis or Dissertation(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2012-01-11 | |||||
| タイトル | ||||||
| タイトル | Design of Microcontroller with Completion Detection Capability by using Dual-Rail Domino Circuit | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源 | http://purl.org/coar/resource_type/c_46ec | |||||
| タイプ | thesis | |||||
| その他のタイトル | ||||||
| その他のタイトル | 2線式ドミノ回路による終了検出型マイクロコントローラの設計 | |||||
| 著者 |
Dia, Kin Hooi
× Dia, Kin Hooi |
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| 著者別名 | ||||||
| 識別子Scheme | WEKO | |||||
| 識別子 | 5980 | |||||
| 姓名 | ディア, キン フイ | |||||
| 著者所属 | ||||||
| 著者所属 | 東京大学大学院工学系研究科電子工学専攻 | |||||
| 著者所属 | ||||||
| 著者所属 | Department of Electronic Engineering, Graduate School of Engineering, The University of Tokyo | |||||
| Abstract | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | A 8-bit non-pipeline microcontroller equipped with completion detection capability is designed by using dual-rail domino circuit. The microcontroller is designed based on the instruction set of Z80 microcontroller. It is implemented with Rohm 0.35μm CMOS technology with chip size of 4.9×4.9mm2, and the measurement results reveal that it could functionally works correctly regardless of the variations due to the instruction dependency, data dependency, and the inter-chip variability. The microcontroller achieves an average speed performance of 23.3ns for evaluation time, and it needs 2.2ns for precharge time at nominal supply voltage of 3.3V. It also exhibits an automatic performance adaptation to the physical properties such as power supply voltage. Along with these, this paper presents a new footless dual-rail domino circuit that efficiently combines a footless dynamic circuit technique with a robust self-timed precharge scheme for high performance VLSI circuit design. Besides, the proposed circuit achieves a whole footless dual-rail domino circuit with the use of the proposed separator. A 20-stage NAND chains are implemented both in 0.15μm SOI CMOS technology and 90nm bulk CMOS technology for performance evaluation. Measurement results reveal that the proposed circuit achieves speed improvement over the circuit implemented with the conventional static CMOS, CPL, dynamic DCVSL, D4L, and DR-domino. | |||||
| 書誌情報 | 発行日 2006-02-03 | |||||
| 日本十進分類法 | ||||||
| 主題Scheme | NDC | |||||
| 主題 | 549 | |||||
| 学位名 | ||||||
| 学位名 | 修士(工学) | |||||
| 学位 | ||||||
| 値 | master | |||||
| 研究科・専攻 | ||||||
| 工学系研究科電子工学専攻 | ||||||
| 学位授与年月日 | ||||||
| 学位授与年月日 | 2006-03-23 | |||||
